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Altera_Forum's avatar
Altera_Forum
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15 years ago

Port map verilog module in vhdl

How can I port map a verilog module/file in an VHDL top module? I've tried the normal VHDL way without any luck. Thanks for any help.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    What do you mean for the normal VHDL way?

    In Quartus there is no problem: you can use the functions in the File menu to create the VHDL component declaration template of a Verilog module (and vice versa).

    If you mean to mix VHDL and Verilog in ModelSim, this is not allowed in Altera Starter Edition, if I remember correctly.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    i don't think you'll be able to use VHDL direct instantiation of a Verilog module, so you will need to include the component declaration as described above