Altera_Forum
Honored Contributor
Honored ContributorPort map verilog module in vhdl
How can I port map a verilog module/file in an VHDL top module? I've tried the normal VHDL way without any luck. Thanks for any help.
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Altera_ForumHonored Contributor
Honored Contributori don't think you'll be able to use VHDL direct instantiation of a Verilog module, so you will need to include the component declaration as described above
