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Altera_Forum
Honored Contributor
13 years agoDid you review the list of errata:
http://www.altera.com/literature/es/es_stratixiv_gx.pdf Search for ATX in the document. There are a few errata listed. I'm not sure if its one that is affecting you. Note the placement restrictions on p11, i.e., ATX PLLs cannot drive all the transceivers blocks on a side, but only the ones right next to it. The GTs have a similar errata. I created a 32 x 10Gbps transceiver design using CMU PLLs and it was acceptable to Quartus. Cheers, Dave