PLL Warnings appearing with Quartus Prime

Hi,

From what I can see in the fitter resource utilization report the three PLLs seem to be implemented correctly. The IPs were re-generated (using Megawizard) when I moved from v15 to Prime v17. The IP components panel says that the IPs are Altera PLL v17.1 and up-to-date.

In my VHDL I copy the component declaration from the .cmp file generated by Megawizard in the declaration section and then I instantiate the component in the behavioral section.

Here again, the design works as expected ! My only concern is about these somehow destabilizing warnings saying that the synthesizer threw away parts of the design !