PLL Tolerance [ppm] in Cyclone V

You are confusing two separate concepts.

There is clock source 'accuracy', which is what the PPM specification represents. For example, you might have a 50MHz oscillator with a +/-100 PPM initial accuracy. So this gives the nominal accuracy that you would measure on a frequency counter, for example.

The PLL will perform an integer multiply / divide on this value to give the output frequency. So do the multiply/divide calculation on the minimum input frequency (50MHz - 100ppm) and on the maximum input frequency (50MHz + 100ppm) to find the PLL output limits.

Now all clock sources have short term jitter characteristics, and PLL circuits have short term jitter characteristics as well. This value of the device will affect the cycle-cycle timing characteristics (ie, between successive rising edges of the clock). Typically given in picoseconds.

Here is an example of using a 50MHz 100ppm source multiplied by 6 to give 300MHz output, and a 150MHz 100ppm source multiplied by 2 to give the same 300MHz output.

As the table shows, the results are EXACTLY the same at the output of the PLL. So using a higher input frequency at the same PPM tolerance does not make a difference on the generated output.

The input jitter of the clock sources effect on the PLL depends on the PLL loop characteristics of the particular FPGA device. That is not as easy to quantify in simple table. The PLL has a filtering effect on the input source jitter, and there is an inherent PLL jitter on the generated output. But since the output frequency is the same the for each PLL case the jitter should be very similar for each.

So long story short just changing the input frequency from 50MHz to something like 150MHz, assuming you want the same output frequency, is a wash. No benefit.