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Altera_Forum's avatar
Altera_Forum
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16 years ago

PLL to PLL for Valid Switchover

I'm trying to perform clock switchover on two clocks that are not within 20% of eachothers frequency. Can you daisy chain the output of a PLL into the second input of a second PLL such that two clocks that were not originally within 20% of eachother are, and reliably perform the switchover function and output status signals? Can't seem to find a block diagram that shows the different sources of inputs to PLLs...

I've tried it in Quartus, but this persists... 

Critical Warning: PLL "asdf:myCHECKPLL|altpll:altpll_component|asdf_altpll:auto_generated|pll1" uses the auto-switchover feature, but the input clock frequencies are too far apart

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    6-15 of the stratix iii handbook seems to indicate i can at least get the output of one to the input of the next. the warning still concerns me.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The auto-switchover feature tries to detect, if the presently selected input clock is invalid and then switches to the alternate source. The detection mechanism is based on both clocks mutually monitoring the others edges and requires both clocks to keep the said frequency ratio.

    An input clock frequency outside the said range would allow no PLL locking anyway, but it also can prevent the switchover circuit from detecting an invalid clock. As an example, if you have a differential clock input with AC coupling but no clock present, the switchover circuit possibly doesn't work correctly, cause input noise is faking an input clock signal.

    A switchover between sources of different frequency should be possible through PLL chaining, with FPGA families that support it.

    P.S.: The warnings are related to possible lock problems in case of excessive jitter. Actually, chained PLLs are often used e.g. with SERDES applications, where a PLL sourced reference clock is feed to a second PLL at the receiver. Even chaining of three PLLs isn't unusual in such applications. As suggested in the device handbook, the chained PLLs should be set a a higher bandwidth to be able to track the input jitter.