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only in very inescapable situations i force myself to understand somebody else's code
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The beauty of someone providing you code that includes a testbench is that you do not really need to start with any understanding. You can run the simulation, look at the waveforms, look at the trace message, and then decide where to start reading to see how it was implemented.
In the case of the ALTPLL_RECONFIG component simulation, there is no synthesis code added, there is merely a simulation of the Altera-provided component. In an ideal world, Altera would provide a nice testbench with every one of their components so that you could unambiguously see how they expect you to use their components. Unfortunately that is not the case, so you should build your own simulation, or hope that someone else has written one and posted it to the forum :)
If you want to learn how to design and build systems, its always worth looking at other peoples code - even it if its only to decide that "that is not the way I would do it".
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after hitting a wall by head through many days i came to the solution: it appears to be that fitter uses these pll post scaler counters (C4,C3,C2,C1,C0) in non orderly manner.
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I recall seeing a warning about this in one of the pieces of documentation I read. Searching through the ALTPLL and ALTPLL_RECONFIG user guide for "Preserve" I do not see a mention of the setting you used. However, in AN367 which is for the Stratix II device I was using, that "feature" is mentioned (see PRESERVE_PLL_COUNTER_ORDER on p14).
http://www.altera.com/literature/an/an367.pdf It is pretty annoying that that critical piece of information is missing from the main user guide. Could you please file a Service Request with Altera and ask them to please add that to their documentation.
Thanks for posting your solution so that others could benefit.
Cheers,
Dave
Honored Contributor
