pll scandataout strange behaviour

I recently wrote a scan-chain controller for the Stratix II device. Before I wrote the controller, I wrote a couple of testbenches; one for the ALTPLL_RECONFIG component, and another that performed direct control of the scan-chain. The testbench was used with the Fast PLL (75-bit scan-chain) and Enhanced PLL (174-bit scan-chain). I'm sure the Cyclone III scan-chain will be similar, even if it is a different length.

Modify these testbench files to use a Cyclone III device and it should be clear what the interface requirements are.

To run the simulation, follow the instructions in readme.txt (duplicated in modified form here)

Altera PLL reconfiguration
--------------------------
10/12/2014 D. W. Hawkins (dwh@ovro.caltech.edu)
This folder contains simulation-only tests of the Altera
ALTPLL and ALTPLL_RECONFIG megafunctions. The tests
targeted the CARMA board Stratix II FPGAs; specifically
the Fast PLL which can be used with the ALTLVDS_RX
component when operated in SERDES mode.
The ALTPLL can be reconfigured via its scan-chain. The
ALTPLL_RECONFIG component provides a wrapper over the
scan-chain making the interface appear more register-like.
The ALTPLL_RECONFIG component is not actually that useful,
since to use it in a Qsys system, you'd need to build an
interface controller - why bother, when you can just
build an interface controller for the scan-chain
directly, eg., see
$VHDL/lib/altera_pll/src/altpll_scanchain_controller.vhd
The code in this folder was used to determine the
appropriate interface waveforms, i.e.,
 * The start of the scan-chain load sequence is;
    - scanread asserted
    - a leading 0 data bit is clocked in, followed
      by the scan-chain data
 * The end of the scan-chain load sequence is;
    - just prior to the clocking of the final scan data
      bit, scanread is deasserted, and scanwrite is
      asserted
    - scanwrite is held asserted until scandone asserts
    - scanwrite is then deasserted and scanclk pulsed
      until scandone deasserts
 * Pulsing scanwrite re-writes the scan data.
    - This is used for output clock phase-shifting
The Stratix II Errata states that scandone may stay low
when performing phase-shifting via pulsing of scanwrite,
however, hardware tests on the CARMA board show it works
correctly (at least for the cases tested). The
SignalTap II logic analyzer traces did not match the
simulation traces, however, scandone does assert and then
deassert several scanclk periods later. This is consistent
with what the altpll_scanchain_controller FSM expects.
-------------------------------------------------------------------
Simulation Instructions
-----------------------
1. Unzip the zip file, eg., into
   c:/temp/altera_pll_reconfig
2. Start Modelsim (Altera Starter Edition)
3. Change directory to the unzipped project
   Modelsim> cd {C:\temp\altera_pll_reconfig}
4. Source the simulation script
   Modelsim> source scripts/sim.tcl
   The final output from that script is a list of the
   testbench procedures. These are Tcl procedures that
   call vsim on the testbench and then populate the
   wave window
  #  Testbench procedure
  #  --------------------
  # 
  #    altpll_reconfig_tb   - ALTPLL + ALTPLL_RECONFIG testbench
  #    altpll_scanchain_tb  - ALTPLL + direct scan-chain control testbench
  # 
5. Run the ALTPLL_RECONFIG testbench
   Modelsim> altpll_reconfig_tb
6. Run the ALTPLL scan-chain control testbench
   Modelsim> altpll_scanchain_tb

Cheers,

Dave