PLL Reconfiguration/Phase Problem

I'm using a Cyclone IV, Quartus 13.1.0, and have designed a reconfigurable PLL that can be programmed for one of four different output frequencies. There are two PLL outputs, FAST & SLOW, the SLOW output is 1/2 the frequency of the FAST output. The problem I'm seeing is that when I reconfigure the PLL the phase relationship between FAST & SLOW is sometimes incorrect, it should be zero. It appears to jump in increments of 1/2 the FAST clock period. Has anyone ever seen this?