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Altera_Forum's avatar
Altera_Forum
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11 years ago

PLL Reconfiguration/Phase Problem

I'm using a Cyclone IV, Quartus 13.1.0, and have designed a reconfigurable PLL that can be programmed for one of four different output frequencies. There are two PLL outputs, FAST & SLOW, the SLOW output is 1/2 the frequency of the FAST output. The problem I'm seeing is that when I reconfigure the PLL the phase relationship between FAST & SLOW is sometimes incorrect, it should be zero. It appears to jump in increments of 1/2 the FAST clock period. Has anyone ever seen this?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Just wonder if you have try to reset the PLL after the reconfiguration? Reset is recommended after reconfiguration to ensure the PLL can function as expected.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    if initial (pre-reconfig) phase shift for both FAST & SLOW is 0 degree, then whatever MNC counter you reconfigure, expected that you will get a 0 degree phase relationship after a RESET.

    what is your initial settings and what did you reconfig? Perhaps i can help you further.