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You're expecting me to read the whole post?
As for the core issue, you state that the PLL lock signal goes high but the PLL does not lock. What symptoms are you seeing to state it's not locking? Is it not outputing a clock, or is the clock drifting, or something like that? Also, does the PLL work if you don't have any reconfiguration(i.e. a fundamental locking issue) or does it occur when adding the dynamic logic(i.e. something going wrong there)?
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As I said below, the clock works for a few cycles and stays high. before the dynamic reconfiguration, the PLL locks without any problem.
It was stated in one of the altera doc that the data is available on the reconfig block input 2 cycles after the address is set. I confimed that and the mif I use are generated by the mega function.
So I am a bit lost
Thanks again
Hakim
Honored Contributor
