PLL problem after power on reset

Hi,

Thanks for all your responses. I'm running the ALT2GXB in XAUI mode. So, in the arriagx, the tx pll/rx pll's generate a 625MHz serial clock and a 156.25MHz enable for the lvds blocks. It's the same on the stratix side. Local loopback always works in the arria's.

In the arria's, the reset is kept on the pll's until there is a stable clock. There is a state machine that generates the resets in the correct sequence for the GXB and I use the same state machine to extend the reset to the rest of the logic, including the pll's. When the pll's come out of reset, there would have been a clock present for quite some time. In the stratix, I don't think it's quite organised that way.

Does a clock source need to be preset at a pll during power-up or is it after it comes out of reset? Or as Kaz says, remove the resets altogether.

I have switch which understands xaui protocol, so I use that for testing. I can never be sure if signal tap is telling me the truth or not.

Regards

MT