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Altera_Forum's avatar
Altera_Forum
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17 years ago

PLL problem after power on reset

Hi, I'm sending data from an arriagx using the lvds block to a stratix fpga, looped through the stratix and back out to the arriagx. There are four lvds blocks involved and each has it's own pl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I guess, it may be a problem of startup order. An Altera PLL is guaranteed to lock at a reproducable phase defined in the PLL parameters, if a stable input clock is present at startup and not interrupted afterwards. This condition may be easily violated when connecting multiple PLLs in bidirectional source synchronous LVDS transmission.

However, you didn't exactly tell the used LVDS clocking scheme.