PLL problem after power on reset

Hi Motah,

I had come across somewhat similar problem. I had a PLL in startix II that was used tol receive a clock from DAC then its output clock(rotated) used to clock data out of fpga to DAC. It caused power-up problems. The phase was unpredictable.

I contacted altera but eventually removed the PLL reset altogether and it was fine.

I must also tell you that I didn't depend on signaltap but on actual signal spectrum after DAC. I don't give too much weight to signaltap in these circumstances.

kaz