Honored ContributorHi :
Is it allowed to configure pll clock outputs as differential mode when the bank IO voltage is 3.3V. If so, does VCCA provide the +2.5V for this kind of LVDS mode? Is it same as the banks assigned to DDR2?
Honored ContributorOutput drivers are powered by bank VCCIO, there's no supported 3.3V differential I/O standard. What you can probably do is to assign fake 2.5 V VCCIO to the bank and use a 2.5 V I/O standard with reduced performance. Particularly a differential standard with external resistors should work.
Honored ContributorIt is worth to try on my demo board. I just have a look at cyclone IV's handbook. It says quartusii places a NOT gate in I/O element to implement this PLL output pair. It is quite similar to Emulated LVDS transmitter on top and bottom banks. Dose the external resistors you mentioned same as the counter measure of Emulated LVDS transmitter? (2 x 120ohm and 1 x 170ohm)
Honored ContributorYes, I meaned a resistor combination similar to the emulated LVDS_E_3R standard. Check if the common mode output voltage with 3.3V VCCIO is in the accepted range of your LVDS receivers, otherwise additional pull-down resistor would be necessary to adjust it.
Honored ContributorGreat help!
