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Altera_Forum
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9 years ago

PLL outputs on 3.3V IO bank of CycloneIV

Hi : Is it allowed to configure pll clock outputs as differential mode when the bank IO voltage is 3.3V. If so, does VCCA provide the +2.5V for this kind of LVDS mode? Is it sa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Yes, I meaned a resistor combination similar to the emulated LVDS_E_3R standard. Check if the common mode output voltage with 3.3V VCCIO is in the accepted range of your LVDS receivers, otherwise additional pull-down resistor would be necessary to adjust it.