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Altera_Forum
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9 years ago

PLL outputs on 3.3V IO bank of CycloneIV

Hi : Is it allowed to configure pll clock outputs as differential mode when the bank IO voltage is 3.3V. If so, does VCCA provide the +2.5V for this kind of LVDS mode? Is it sa...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Output drivers are powered by bank VCCIO, there's no supported 3.3V differential I/O standard. What you can probably do is to assign fake 2.5 V VCCIO to the bank and use a 2.5 V I/O standard with reduced performance. Particularly a differential standard with external resistors should work.