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Altera_Forum
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9 years ago

PLL outputs on 3.3V IO bank of CycloneIV

Hi : Is it allowed to configure pll clock outputs as differential mode when the bank IO voltage is 3.3V. If so, does VCCA provide the +2.5V for this kind of LVDS mode? Is it sa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

It is worth to try on my demo board. I just have a look at cyclone IV's handbook. It says quartusii places a NOT gate in I/O element to implement this PLL output pair. It is quite similar to Emulated LVDS transmitter on top and bottom banks. Dose the external resistors you mentioned same as the counter measure of Emulated LVDS transmitter? (2 x 120ohm and 1 x 170ohm)