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Altera_Forum
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12 years ago

PLL Megafunction actual clock frequency

Hi, I am using the Altera PLL Megafunction to generate 6 different clocks (100, 125, 200,50, 1MHz) with a reference clock of 100 MHz. I set all the frequencies correctly except for the 1 MHz c...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

If you don't need special clock shift,

you can use divider on flip-flop, example (verilog)

wire clk_200; // (200MHz fom pll)

reg clk_100;

reg clk_50;

always @(posedge clk_200)

begin

clk_100 <= ~clk_100;

end

always @(posedge clk_100)

begin

clk_50 <= ~clk_50;

end