PLL Megafunction actual clock frequency

Question

Hi,

I am using the Altera PLL Megafunction to generate 6 different clocks (100, 125, 200,50, 1MHz) with a reference clock of 100 MHz. I set all the frequencies correctly except for the 1 MHz clock. In the actual clock frequency parameter, i get 1.9 MHz when I enter 1 MHz. When I tried to make a second PLL megafunction that has only one output clock of 1 MHz, it also didn't work and i got 1.17 MHz ! How can i solve this ?

Thanks in advance.

altera_forum · Answer

You can: 1. change Altera device 2. using pll to get 200, 125, 1MHz; and get 100, 50 MHz from 200MHz using the divider

altera_forum · Answer

do u mean using the divider "C parameter" in PLL or u mean I implement a frequency divider?

altera_forum · Answer

If you don't need special clock shift,

you can use divider on flip-flop, example (verilog)

wire clk_200; // (200MHz fom pll)

reg clk_100;

reg clk_50;

always @(posedge clk_200)

begin

clk_100 <= ~clk_100;

end

always @(posedge clk_100)

begin

clk_50 <= ~clk_50;

end

altera_forum · Answer

Yeah but I was thinking that using such frequency dividers would lead to timing violations and that it would be better to use a second PLL.

altera_forum · Answer

You didn't tell about the involved Altera device so we don't even know if the PLL supports frequencies down to 1 MHz. But apparently, there's a conflict with available PLL parameters.

It ususally doesn't make sense to use low requencies like 1 or 2 MHz as design clock. You can use a regular design clock in the 10 to 50 MHz range and generate a 1 MHz clock enable by a divider.

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PLL Megafunction actual clock frequency

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