Forum Discussion
Honored ContributorPLL Megafunction actual clock frequency
Hi,
I am using the Altera PLL Megafunction to generate 6 different clocks (100, 125, 200,50, 1MHz) with a reference clock of 100 MHz. I set all the frequencies correctly except for the 1 MHz clock. In the actual clock frequency parameter, i get 1.9 MHz when I enter 1 MHz. When I tried to make a second PLL megafunction that has only one output clock of 1 MHz, it also didn't work and i got 1.17 MHz ! How can i solve this ? Thanks in advance.9 Replies
Altera_ForumYou can:
1. change Altera device 2. using pll to get 200, 125, 1MHz; and get 100, 50 MHz from 200MHz using the divider- Altera_Forum
do u mean using the divider "C parameter" in PLL or u mean I implement a frequency divider?
- Altera_Forum
If you don't need special clock shift,
you can use divider on flip-flop, example (verilog) wire clk_200; // (200MHz fom pll) reg clk_100; reg clk_50; always @(posedge clk_200) begin clk_100 <= ~clk_100; end always @(posedge clk_100) begin clk_50 <= ~clk_50; end - Altera_Forum
Yeah but I was thinking that using such frequency dividers would lead to timing violations and that it would be better to use a second PLL.
- Altera_Forum
You didn't tell about the involved Altera device so we don't even know if the PLL supports frequencies down to 1 MHz. But apparently, there's a conflict with available PLL parameters.
It ususally doesn't make sense to use low requencies like 1 or 2 MHz as design clock. You can use a regular design clock in the 10 to 50 MHz range and generate a 1 MHz clock enable by a divider. - Altera_Forum
It looks like you're using a Cyclone V PLL, whose minimum output frequency is 5MHz.
Like FvM stated - don't drive logic with such a slow clock. Use a faster one (e.g. 100MHz), count the appropriate number of clock cycles (e.g. 100) and perform an operation each time your counter wraps. If you need a 1MHz 'clock' signal out of a pin you can generate it in a similar way, by counting clock cycles and toggling an output register appropriately. - Altera_Forum
This forum post is very informational and gives some additional information on generating divided clocks:
http://www.alteraforum.com/forum/showthread.php?t=2388 - Altera_Forum
I am using Arria v. I was just wondering why the 1 MHz that I had in the PLL turns to 1.9 MHz(actual clock frequency) when I add the 200 MHz clock. It seems the number of output clocks and their values influence each other. Thanks a lot everyone for your help.
- Altera_Forum
Try switching "PLL Mode" to Fractional. In Integer mode, you are stuck with the K divider at 1 in the GUI so VCO minimum of 600MHz feeds the dividers, which each have maximum value 512 so the minimum output is the 1.17MHz you saw.
It will work for your single output of 1.000MHz But with the other clocks added, it looks like 125MHz is going to be the problem. The PLL is described in: http://www.altera.com/literature/hb/arria-v/av_52004.pdf And page 4-27 is probably what you're most interested in while trying to understand what the wizard is producing for you.
