Forum Discussion
Altera_Forum
Honored Contributor
12 years agoYou didn't tell about the involved Altera device so we don't even know if the PLL supports frequencies down to 1 MHz. But apparently, there's a conflict with available PLL parameters.
It ususally doesn't make sense to use low requencies like 1 or 2 MHz as design clock. You can use a regular design clock in the 10 to 50 MHz range and generate a 1 MHz clock enable by a divider.