Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

PLL locking and reset generation in Cyclone III

Hi everyone, I'm designing a board using one Cyclone 3 part on it. I'm defining the reset circuit and some questions come to my mind. (I'm new to Cyclone 3 and FPGA so these questions may seem ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

As far as I understand, asynchronous resets can make timing closure a bit more dificult.

Thus, as much as possible, I use synchronous resets.