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Altera_Forum
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11 years ago

PLL Locking - Transient input clock

Hello,

I am hoping someone can offer a bit of advice with respect to using a PLL to lock to a clock that is transient. Currently I have the differential clock signal entering on an clock input pin in an Arria V device. My problem is that the clock is switched off by the source between data packets. There is a small window of about 150ns in which the clock is running, prior to data begining. I was hoping to use Altera PLL to lock to this clock when its available, in order to take advantage of the verious skew related options that are offered, so that the clock is phase adjusted at the PLL output to be syncronous with the pin's input.

However, after playing around with the PLL, the lock time is just too slow, so that by the time the PLL has locked the data has already begun to transmit. The obvious solution is to use the input clock directly, and adjust the data lines for any skew on the clock line. This is the approach I am currently taking, but I would love to know if there is any technique to enable quicker locking on the PLL.

Additionally, as the input data is serial, I would like to also try using the transceivers to receive the data, but I am still a bit confused on whether or not I can do this with a clock that is transient. It seems that I could provide my own internal clock to the transciever and use the CDR stuff to recover the clock from the input data alone? and ignore the clock that is transmitted with the data?

Any advice or comments is greatly appreciated.

rma.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I doubt you can make this work with an internal PLL. One option might be an external PLL with local oscillator (VCO or VCXO). The PLL phase detector would be in the FPGA with the rest of the components external. The idea would be to have the local oscillator track your gated Rx data clock. The local oscillator phase and frequency would be "pulled in" while the Rx clock is running, then free-run (and drift) when the Rx clock is gated between packets. With the right loop filter characteristics you may be able to make it work and minimize the drift of the local oscillator between packets. This would obviously require a board spin and a fair amount of PLL design expertise, so sticking with what you're already doing is probably your best option if it's working.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The Arria V PLL would require some time to relock to the input clock. From the Arria V device datasheet - > Table 26. PLL Specifications for Arria V Devices, it seems like the lock time is up to 1ms. You could consider using transceiver since transceiver only require you to feed it with data. The CDR will recover the required clock from the serial data.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    JFYI, you can have the PLL lock faster by setting to High BW, provided you have a clean clock that is not jittery.

    However, it will still take some time until it locks.

    Furthermore, when there is no refclk (since your clock is transient), your PLL will lose lock and then it takes time to re-lock.

    So still it might not be the best solution to your problem.