PLL Locking - Transient input clock

I doubt you can make this work with an internal PLL. One option might be an external PLL with local oscillator (VCO or VCXO). The PLL phase detector would be in the FPGA with the rest of the components external. The idea would be to have the local oscillator track your gated Rx data clock. The local oscillator phase and frequency would be "pulled in" while the Rx clock is running, then free-run (and drift) when the Rx clock is gated between packets. With the right loop filter characteristics you may be able to make it work and minimize the drift of the local oscillator between packets. This would obviously require a board spin and a fair amount of PLL design expertise, so sticking with what you're already doing is probably your best option if it's working.