Honored ContributorHi,
When i use Altpll to design a PLL, how do i know where the designed PLL will be? Or, how do i assign a PLL to be used at a specific location so that i can assign a input pin for it? Thanks Yaoting I am using Cyclone IV GX, EP4CGX150DF27C7
Honored ContributorHi, one way is to create a LogicLock Region at the location where you want the PLL to be, and then you can assign this PLL to this LogicLock Region. I do it like this, but maybe there is another better way.
Honored ContributorIt sounds like you currently have free choice of both PLL and clock input pin. If you chose a sensible clock input pin - i.e. a dedicated clock input - it is highly likely that Quartus will make use of the most sensible PLL, the one whose routing from the clock input pin is shortest.
Once you've compiled your design, and established Quartus has placed your PLL appropriately, you can use Chip Planner to lock it's position. If Quartus has chosen poorly (unlikely) use Chip Planner to move it. See here for guidance: http://www.altera.co.uk/literature/hb/qts/qts_qii52006.pdf (http://www.altera.co.uk/literature/hb/qts/qts_qii52006.pdf) Regards, AlexHonored ContributorHi,
Thank you, guys for your responses to my question. I got the resolution from an Altera engineer. The following link might be your reference. http://www.altera.com/support/kdb/solutions/rd07152010_131.html Appreciate a lot.
