PLL location assignment

It sounds like you currently have free choice of both PLL and clock input pin. If you chose a sensible clock input pin - i.e. a dedicated clock input - it is highly likely that Quartus will make use of the most sensible PLL, the one whose routing from the clock input pin is shortest.

Once you've compiled your design, and established Quartus has placed your PLL appropriately, you can use Chip Planner to lock it's position. If Quartus has chosen poorly (unlikely) use Chip Planner to move it. See here for guidance:

http://www.altera.co.uk/literature/hb/qts/qts_qii52006.pdf (http://www.altera.co.uk/literature/hb/qts/qts_qii52006.pdf)

Regards,

Alex