PLL dedicated external clock output pins in cyclone II EP2C20F484c7 FPGA

Actually, ALTPLL megafunction is having c0,c1,c2 as PLL clock outputs for cyclone II EP2c20F484c7. The dedicated PLL clock output pins are (PLL1_OUTp, PLL1_OUTn), (PLL2_OUTp, PLL2_OUTn), (PLL3_OUTp, PLL3_OUTn), (PLL4_OUTp, PLL4_OUTn) (differential output).

I have access only to the two 40 pin expansion headers(which connects 72 FPGA pins) since it is a starter board. (PLL2_OUTp, PLL2_OUTn) pins are connected to one of the expansion headers. So, i tried to assign PLL2_OUTp pin to PLL clock output c2 since i need only single ended o/p & c2 is the clock output which drives the external clock o/p. Still, the same warning comes while compilation

warning: pll "pll:u3|altpll:altpll_component|pll" output port clk[0] feeds output pin "c2" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. use pll dedicated clock outputs to ensure jitter performance

Please give your suggestions on this.