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mdidomenico3
New Contributor
New ContributorPLL Compensation Mode explanation
I have a design in which I am attempting to transfer data from clk1 to clk2, where clk1 is an output from an upstream PLL, drives core logic, and is the input ref clock to a downstream PLL, which gen...
lixy
Contributor
ContributorHi mdidomenico3,
When doing cascading, normally we need to treat these two clocks as asynchronous whichever mode you select. You may just choose Normal Mode. But timing must be ensured in RTL design, rather than simply relying on the compensation mechanism of PLL.
Best Regards,
Xiaoyan
