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mdidomenico3's avatar
mdidomenico3
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1 year ago

PLL Compensation Mode explanation

I have a design in which I am attempting to transfer data from clk1 to clk2, where clk1 is an output from an upstream PLL, drives core logic, and is the input ref clock to a downstream PLL, which gen...
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lixy's avatar
lixy
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1 year ago

Hi mdidomenico3,


May I know which device are you using?

What is the mode selected for the fPLL now?


Best Regards,

Xiaoyan


  • mdidomenico3's avatar
    mdidomenico3
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    1 year ago

    The fPLL is generated by a transceiver IP core, so I'm not sure what settings are in use, and the device family is Stratix 10.