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mdidomenico3
New Contributor
New ContributorPLL Compensation Mode explanation
I have a design in which I am attempting to transfer data from clk1 to clk2, where clk1 is an output from an upstream PLL, drives core logic, and is the input ref clock to a downstream PLL, which gen...
mdidomenico3New Contributor
New ContributorI'd like to add that the upstream PLL is an fPLL, so clk1 is a clock generated from an fPLL, not an IO PLL.
