Forum Discussion

mdidomenico3's avatar
mdidomenico3
Icon for New Contributor rankNew Contributor
10 months ago

PLL Compensation Mode explanation

I have a design in which I am attempting to transfer data from clk1 to clk2, where clk1 is an output from an upstream PLL, drives core logic, and is the input ref clock to a downstream PLL, which gen...
Configuration
mdidomenico3's avatar
mdidomenico3
Icon for New Contributor rankNew Contributor
10 months ago

I'd like to add that the upstream PLL is an fPLL, so clk1 is a clock generated from an fPLL, not an IO PLL.