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Altera_Forum
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9 years ago

PLL clock switchover with automatic derivation of PLL clocks is not working

Hi all, I'm using a Cyclone V and need to switch between two input clocks. The clocks have the same parameters. I adhered to the timequest cookbook which says the following: #create a 10...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Thanks for your reply!

Both clocks are connected directly to the PLL. From dedicated clock input pins of the FPGA to "refclk" and "refclk1" inputs of the PLL. To switch from one clock to the other I'm using the clock switchover feature of the PLL. So my logic isn't really involved in that whole clock thing. Its job is just to set the "extswitch" input of the PLL to logic '1' for a certain time whenever I want to switch the clocks. Until that the PLL defaults to "refclk".