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Altera_Forum
Honored Contributor
9 years agoHow are you selecting the input clock to the PLL? That logic may be why derive_pll_clocks isn't working. Can you post the HDL code? Normally, clock inputs make direct connections to PLLs.
How are you selecting the input clock to the PLL? That logic may be why derive_pll_clocks isn't working. Can you post the HDL code? Normally, clock inputs make direct connections to PLLs.