I am fighting Pin Planner at every turn. In my QSF file, I have the following: set_location_assignment PIN_T22 -to "HSMC_RX_D_N(n)" set_instance_assignment -name IO_STANDARD LVDS -to "HSMC_RX_D_N(n)" When I import assignments and view them in either Assignment Editor or Pin Planner, the signals are not set to LVDS, they are not differential. However, when I use Pin Planner and set a signal as LVDS, it then sets the negative pair as the current signal with an extra (n). So my "HSMC_RX_D_N[15](n)" becomes "HSMC_RX_D_N[15](n)(n)" and "HSMC_RX_D_P[15]" becomes "HSMC_RX_D_P[15](n)". And then Pin Planner creates several "fake" signals N(n)(n) or P(n) that have the same location as the actual signals. Then when I compile the design, I get location errors. I'm using "iobuf" from the megawizard to make the differential signals single ended. My two questions: 1.) How do i properly (manually even) set the signals in my QSF file so they they import properly (LVDS, differential, paired). 2.) How do I make Pin Planner stop being so mean to me? Thanks

--- Quote Start --- How do I make Pin Planner stop being so mean to me? --- Quote End --- You cannot. Its sole purpose in life is to frustrate you :) For LVDS signals, you only need to assign the pin and IO_STANDARD to the positive side of the pair, and Quartus will infer the negative pin assignment. This means your top-level entity does not need to include your two signals, i.e., HSMC_RX_D_P and HSMC_RX_D_N, you can just call it HSMC_RX_D and make it LVDS. You then do not need an iobuf at the top-level of your design. There are other solutions, but this one results in the least code :) Cheers, Dave

I think I am confused. At my top level I have: input HSMC_CLKIN2, //Serial CLK IN_N input [16:0] HSMC_RX_D I then removed all assignments and re-imported my QSF that only contains the positive locations for HSMC_RX_D. Pin Planner automatically generates the _P and _N(n) locations. I removed the buffer from the top level. The only thing I'm trying to do is see the single ended signals. HSMC_RX_D[0] -> GPIO[0] -- there's no logic, no registers, no clocking. I had this working before by magic but I've since destroyed that code. But, I know the problem lies in the LVDS setting. Also, the signals are not LVDS. When I set them to LVDS, (n)(n) appears, but it compiles w/o error. But still no signals on the GPIO.

--- Quote Start --- I think I am confused --- Quote End --- No problem, lets try to resolve that ... :) --- Quote Start --- The only thing I'm trying to do is see the single ended signals. --- Quote End --- Hang on, you're changing your requirement here ... Your interface has to either be defined as differential LVDS, in which case you cannot view the output signals unless you have a termination resistor across the output pair, or you want your signals as single-ended. So what is your requirement? Cheers, Dave

The signals are coming into the FPGA as differential and I have control over the ADC that is attached via the HSMC connector to enable 94 Ohm (and other values) resistors for termination. So, I want to handle single ended signals within the FPGA, so they need to go through a buffer to become single ended, yes?

--- Quote Start --- The signals are coming into the FPGA as differential and I have control over the ADC that is attached via the HSMC connector to enable 94 Ohm (and other values) resistors for termination. --- Quote End --- That does not make sense. If the ADC is sending LVDS signals to the FPGA, then the termination resistor is required at the end of the transmission line, i.e., at the FPGA. Its possible that your ADC has the resistor option for another logic standard, eg., source terminations. What is the part number of the ADC? --- Quote Start --- So, I want to handle single ended signals within the FPGA, so they need to go through a buffer to become single ended, yes? --- Quote End --- No, you can define a receiver port as differential LVDS, and then only have the differential receiver output defined in your top-level entity, i.e., you can have a signal defined as my_lvds in your top-level entity and can consider that to be your differential receiver output and then in your pin assignments, the pin named my_lvds is the positive input and the pin named my_lvds(n) is the negative input. Yeah, its not exactly obvious ... and its a little confusing ... Which FPGA board are you using? You need to make sure your FPGA supports differential LVDS termination, or that it has termination resistors on the board. Cheers, Dave

Pin Planner LVDS Differential Pair Selection

13 Replies

Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
I'm not afraid of actually soldering, it's just they're super tiny components. And I don't want to solder them only to have to remove them because the FPGA board is used for something else.

--- Quote End ---

I doubt they are that small ... I was soldering 0201 (1mm x 0.5mm) parts last week ... those things are too small, so I'll make sure to stick with 0402 next time I design a board :)

Removal is pretty easy, you just wipe a hot soldering iron over both ends of the part and they come off really easily.

Like I said, so long as you're not trying to do performance measurements, you're probably fine leaving the terminations off.

--- Quote Start ---

The Pin Planner tool keeps locking me out from making changes after I select LVDS. Either it will prevent me from changing something (ignore my change) or prevent me from deleting something.
--- Quote End ---

Go to the "Assignments Editor" and make the edits there.

You can also go to "Project->Generate Tcl File for Project", edit that file (remove the redundant (n) assignments), then use "Assignments->Remove Assignments" and remove all assignments, and then source the edited Tcl file.

I generate all my projects by sourcing Tcl files, rather than the GUI. It makes it much easier to create designs. Take a look at the attached example. It includes differential LVDS constraints. Look at the constraints file in scripts/constraints.tcl, and look at the "Project->Generate Tcl File for Project" script in qwork/s4gxdk.tcl to see how those constraints resolve to Altera's constraints.

Cheers,
Dave
s4gxdk_basic.zip40 KB
Altera_Forum
Honored Contributor
12 years ago
Thank you so much for the files. I will be sure to put them to good use! I was trying to use import / export from the assignments tab and was annoyed that it wasn't working.

Thanks again.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
Thank you so much for the files. I will be sure to put them to good use!

--- Quote End ---

Ask questions if you wonder why I did something the way I did.

My scripts should be fairly obvious once you compare them to the Altera generated script, i.e., mine are more concise and readable :)

--- Quote Start ---

I was trying to use import / export from the assignments tab and was annoyed that it wasn't working.

--- Quote End ---

Tcl scripting is the way to go to control Quartus and Modelsim.

Cheers.
Dave

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Pin Planner LVDS Differential Pair Selection

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