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Altera_Forum's avatar
Altera_Forum
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13 years ago

Pin assignments DE4

Hi to all,

I have a DE4 Development and Education Board. I'm trying to make a simple project consists of a CPU, an on-chip memory, a jtag-uart, a flash memory (Flash Memory Interface (CFI)), a tristate bridge and an 8-bit PIO for the LEDs. I have problems when I try to assign the pins of the flash memory.

Even if I select in the settings of the CFI 25 bits for addresses:

https://www.alteraforum.com/forum/attachment.php?attachmentid=7755

In the pin planner I find 26-bit address width:

https://www.alteraforum.com/forum/attachment.php?attachmentid=7756

Also in the pin planner are missing some control pins shown in the manual of DE4:

  • flash_clk

  • flash_reset_n

  • flash_ce_n

  • flash_oe_n

  • flash_we_n

  • flash_adv_n

  • flash_rdy_bsy_n

  • flash_wp_n

Could you help me to assign the pins of the flash memory?

Also, could you help me to select the setup time, the wait-state time and the hold time of the flash memory?

Thank you so much.

BR,

Umberto.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    You have specified your data width as 16 bits. The address range will be based on the number of bytes (8-bit) available in the memory. So, that is why you have one more address line as compared to what you're expecting.

    Assuming your flash device's data bus is 16-bits wide, ignore the least significant address bit (bit 0).
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Regarding the setup times etc - if you're using a standard Altera development board you should be able to specify the FLASH part used in Qsys when you add the FLASH peripheral to your project. Assuming that is the case that library model will setup all the timing parameters for you.

    If you want to do it manually then you'll have to refer to the manufacturers data sheet for the particular FLASH part in question.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hi a_x_h_75,

    thank you for your support.

    Regarding the control signals, how should I proceed?

    Thank you again.

    BR,

    Umberto
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I think you do have the correct set of signals in your pin planner for a CFI FLASH interface.

    select_n_to_the_cfi_flash <-> flash_ce_n

    read_n_to_the_cfi_flash <-> is flash_oe_n

    write_n_to_the_cfi_flash <-> is flash_we_n

    The address and data ports are also clearly there.

    The other signals shouldn't be needed for a standard CFI.

    flash_reset_n can be driven by your system reset (assuming you have one).

    flash_wp_n can be permanently driven high.

    I'm not sure why there is a flash_clk. CFI FLASH devices don't use a clock. The same applies to flash_adv_n.

    Regards,

    Alex