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Altera_Forum's avatar
Altera_Forum
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12 years ago

Pin assignments DE4

Hi to all, I have a DE4 Development and Education Board. I'm trying to make a simple project consists of a CPU, an on-chip memory, a jtag-uart, a flash memory (Flash Memory Interface (CFI)), a tri...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I think you do have the correct set of signals in your pin planner for a CFI FLASH interface.

select_n_to_the_cfi_flash <-> flash_ce_n

read_n_to_the_cfi_flash <-> is flash_oe_n

write_n_to_the_cfi_flash <-> is flash_we_n

The address and data ports are also clearly there.

The other signals shouldn't be needed for a standard CFI.

flash_reset_n can be driven by your system reset (assuming you have one).

flash_wp_n can be permanently driven high.

I'm not sure why there is a flash_clk. CFI FLASH devices don't use a clock. The same applies to flash_adv_n.

Regards,

Alex