Honored Contributor
Honored ContributorI think you do have the correct set of signals in your pin planner for a CFI FLASH interface.
select_n_to_the_cfi_flash <-> flash_ce_n read_n_to_the_cfi_flash <-> is flash_oe_n write_n_to_the_cfi_flash <-> is flash_we_n The address and data ports are also clearly there. The other signals shouldn't be needed for a standard CFI. flash_reset_n can be driven by your system reset (assuming you have one). flash_wp_n can be permanently driven high. I'm not sure why there is a flash_clk. CFI FLASH devices don't use a clock. The same applies to flash_adv_n. Regards, Alex
