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Altera_Forum
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18 years ago

Pin assignment conflict with Stratix II GX

I've been working on a design project in Quartus (which I'm not extraordinarily familiar with) and am having some difficulties with assigning pinouts for a Stratix II GX on a transceiver development ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

I ever used the same FPGA and I remenber I set outputs of cdr(for example:rx_dataout) as virtual pins(because you only have a top design, and it is a black box), otherwise Quartus would report errors, which I didn't understand. You can try it.