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Altera_Forum
Honored Contributor
19 years agoPin assignment conflict with Stratix II GX
I've been working on a design project in Quartus (which I'm not extraordinarily familiar with) and am having some difficulties with assigning pinouts for a Stratix II GX on a transceiver development ...
Altera_Forum
Honored Contributor
19 years agoYou may have locked the internal placement of entities in addition to the i/o pins. Open the assignment editor (CNTL-SHIFT-A) then use the "Category" pulldown to set the category to "All - Locations". Scroll through the spreadsheet of assignments; you should see pin assignments (net name then "PIN_") but no internal assignments. If there are internal assignments then delete them. Close the assignment editor (say "Yes" to saving changes when prompted) and recompile. This should resolve the conflicting assignment which attempted to lock a gigabit transceiver (GXB) to a set internal location that was contradictory to the assigned pin locations.