New ContributorPHYLite LVDS input
Hi All,
I'm trying to integrate AD9613 ADC (250 MHz LVDS DDR interface) to Cyclone 10 GX device and I would appreciate any help on fixing timing for that.
I've tried to implement the interface using GPIO first, passing clock through "source-synchronous" PLL first (+ a manually adjusted phase shift). For my best attempt (using 900 ps shift), TimeQuest shows slacks circa -0.6 ns both on Setup and Hold in the slow corner. Using different phase shift values, I can move slacks more to Setup or more to Hold, but total slack is more than 1 ns (which I believe is unacceptable).
Reading forums and docs (especially AN 756) I found that GPIO could be simply too slow for implementing 250 MHz input and that PHYLite core usage is recommended.
However, I can't figure out how to use PHYLite in my case. Please would anyone help.
In particular, I'm lost with:
1. How to setup LVDS inputs with PHYLite?
AN 756 (1.4.4) says "You can manually set the pin to use 3.0V/2.5V I/O standard through the Quartus Prime assignment editor".
I've done that (also put IO Standard = None in PHYLite). Fitter now gives "Error(16680): I/O pin DATA_p_6(n) has the LVDS I/O standard assigned to it, however the I/O lane cannot contain pins with the LVDS I/O standard. Modify your design so that pins in the I/O lane are not assigned the LVDS I/O standard."
2. Do I have to physically pass the same signal (ADC clock) through 2 separate IO buffers (2 separate pins)?
If I simply connect DCO_p (ADC clock) both to strobe and ref_clock of PHYLite (as in AN 756 figure 4), fitter complains about incorrect IO buffer configuration. This can be fixed if I pretend to use separate clock and strobe signals.
Any help would be greatly appreciated.
Sincerely,
Anatoly
Details:
The ADC is running at 250 MHz, LVDS DDR interface (4 ns period, 2 ns unit). Clock (DCO pins) is delayed after DATA for 0.4..1.0 ns (0.7 +/- 0.3 ns). Thus, the interface is not "center-aligned", but close to it.
Based on AN 433 I've put the following constraints (I would also appreciate if anyone would check if those constraints are correct):
<code>
set adcPeriod 4.000
# tSkew is 0.4 - 0.7 - 1.0 ns (min - typical - max). This equals to 0.7 ns shift +/- 0.3 skew.
# Virtual ADC clock (edge-aligned with data)
create_clock -name adcVirtualClk -period $adcPeriod
# DCO clock
create_clock -name adcDry -period $adcPeriod -waveform { 0.7 2.7 } [get_ports {DCO_p}]
# Skew method delays (see p. 49)
set_input_delay -clock adcVirtualClk -max 0.3 [get_ports DATA_*]
set_input_delay -clock adcVirtualClk -min -0.3 [get_ports DATA_*] -add_delay
set_input_delay -clock adcVirtualClk -clock_fall -max 0.3 [get_ports DATA_*] -add_delay
set_input_delay -clock adcVirtualClk -clock_fall -min -0.3 [get_ports DATA_*] -add_delay
# Set false path (see p. 51-52)
set_false_path -setup -fall_from [get_clocks adcVirtualClk] -rise_to [get_clocks adcDry]
set_false_path -setup -rise_from [get_clocks adcVirtualClk] -fall_to [get_clocks adcDry]
set_false_path -hold -fall_from [get_clocks adcVirtualClk] -fall_to [get_clocks adcDry]
set_false_path -hold -rise_from [get_clocks adcVirtualClk] -rise_to [get_clocks adcDry]
</code>
