PHYLite LVDS input

Hi Ash_R,

there is almost no logic yet, just a LED driver to make the input used (not optimized out).

The code is below.

ADC clock (DCO_p/DCO_n) is first fed into IOPLL (source-synchrounous compensation mode, +700 ps phase shift, 250 MHz in, 250 MHz out) and then driven to GPIO IP instance (data bits are in DATA_X_p/DATA_X_n).

Attached are reports for the "Slow 100C" corner, same pin (DATA_10). "Slow -40C" is worse (-0.702 Setup, -0.435 Hold), Fast corners are better.

<code>

///////////////////
// ADC input

wire [23:0] adcRaw;
wire adcLocked;
wire adcClock;
wire adcRawValid;

adc_pll adcClockPll (
.locked(adcLocked), // locked.export
.outclk_0(adcClock), // outclk0.clk
.refclk(DCO_p), // refclk.clk
.rst(~startUpReset_n) // reset.reset
);

adc_gpio adcInput (
.ck(adcClock), // ck.export
.dout(adcRaw), // dout.export
.pad_in({
DATA_p_0, DATA_p_1, DATA_p_2, DATA_p_3,
DATA_p_4, DATA_p_5, DATA_p_6, DATA_p_7,
DATA_p_8, DATA_p_9, DATA_p_10, DATA_p_11
}), // pad_in.export
.pad_in_b({
DATA_n_0, DATA_n_1, DATA_n_2, DATA_n_3,
DATA_n_4, DATA_n_5, DATA_n_6, DATA_n_7,
DATA_n_8, DATA_n_9, DATA_n_10, DATA_n_11
}) // pad_in_b.export
);

assign adcRawValid = adcLocked;

assign FPGA_LED1 = (adcRaw > 24'hFF00FF); // Make ADC data used (prevent optimizing-out)

</code>

Related pin-out:

<code>

#######################3
## BANK 2A

set_location_assignment PIN_Y1 -to DATA_n_6
set_location_assignment PIN_Y2 -to DATA_p_6
set_location_assignment PIN_Y6 -to DATA_n_3
set_location_assignment PIN_Y7 -to DATA_p_3
set_location_assignment PIN_AA7 -to DATA_n_1
set_location_assignment PIN_AA8 -to DATA_p_1
set_location_assignment PIN_V8 -to DATA_n_7
set_location_assignment PIN_U8 -to DATA_p_7
set_location_assignment PIN_AB1 -to DATA_n_4
set_location_assignment PIN_AA1 -to DATA_p_4
set_location_assignment PIN_V2 -to DATA_n_11
set_location_assignment PIN_W2 -to DATA_p_11
set_location_assignment PIN_T1 -to DATA_n_10
set_location_assignment PIN_R1 -to DATA_p_10
# set_location_assignment PIN_V1 -to DCO_n
set_location_assignment PIN_U1 -to DCO_p
set_location_assignment PIN_V3 -to DATA_n_9
set_location_assignment PIN_U3 -to DATA_p_9
set_location_assignment PIN_AA4 -to DATA_n_5
set_location_assignment PIN_AB3 -to DATA_p_5
set_location_assignment PIN_W3 -to DATA_n_8
set_location_assignment PIN_W4 -to DATA_p_8
set_location_assignment PIN_AB4 -to DATA_n_2
set_location_assignment PIN_AB5 -to DATA_p_2
set_location_assignment PIN_AB9 -to DATA_n_0
set_location_assignment PIN_AB8 -to DATA_p_0

set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_0 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_0 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_1 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_1 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_2 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_2 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_3 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_3 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_4 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_4 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_5 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_5 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_6 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_6 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_7 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_7 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_8 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_8 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_9 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_9 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_10 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_10 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_n_11 -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DATA_p_11 -entity Main
# set_instance_assignment -name IO_STANDARD LVDS -to DCO_n -entity Main
set_instance_assignment -name IO_STANDARD LVDS -to DCO_p -entity Main

</code>

Project settings:

<code>

set_global_assignment -name DEVICE 10CX220YU484I6G
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL ON
set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING ON
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION ON
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON

set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name FAST_PRESERVE OFF -entity main
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
set_global_assignment -name FLOW_ENABLE_EARLY_PLACE ON
set_global_assignment -name VERILOG_FILE main.v
set_global_assignment -name SDC_FILE main.sdc

</code>