PHYLite LVDS input

Hi Ash_R_Intel,

thank you for your answer, I will re-read these docs.

Should I be able to close 250 MHz timing using GPIO Intel FPGA IP?

So far the best I could get was [-0.72 Setup slack, -0.286 Hold slack] for "Slow 100C" corner (so I need about +1 ns into valid data window). Any clue on what is to be tried?

Please would you also confirm that:

1. It is not possible to use PHYLite core with LVDS inputs (need to convert them to something like HSTL on the board level).

2. I need both clock and strobe come from outside of the chip, if using PHYLite

Thanks in advance,

Anatoly

P.S. the chip is 10CX220YU484I6G