Occasional Contributor
Regular ContributorHi Eugeny,
The user guide, Generic Serial Flash Interface Intel® FPGA IP User Guide may help you. Below is the link:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-gen-sfi.pdf
Let us know if this helps.
Regards
Occasional ContributorHello, thank you very much for the document.
Magically the "cycloneii_asmiblock" started functioning properly, and I was able to access (read) flash with up to 45 MHz clock speed. Unfortunately it is not enough and I need it at 75 MHz, but was unable to achieve this speed - either because of board layout, 10 pF caps/BAT54s on the lines (per datasheet recommendation) or just because pins do not support this speed.
Considered using W25Q128FV with "Fast read dual I/O" command, but it appeared that in AS configuration mode the data pins are only in one mode input or output, and it not possible to switch ASDO pin to input mode. Can not get why is this because FPGA must not need configuration device after configuration is finished (because of partial reconfiguration capability?).
