Occasional Contributor
Occasional Contributor1. Referring to this documentation (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-opae-nwi-d5005.pdf), yes i'm using L/H-Tile Native PHY, although i can't access the IP directly in Quartus.
2. I'm using quartus version 19.2.0 Build 57 Pro Edition. This is the default quartus version when configuring the tools to use with Stratix 10 PAC.
3. Apparently with AFU the simulation is done via ASE, but when using HSSI, ASE is not available. So I haven't been able to check from the simulation. Is there any other way for me to try this?
4. serial loopback is asserted when lockedtodata and lockedtoref are both 0. It happened after analogreset falling edge and digitalreset_stat rising edge. After a while the rx_data_valid is asserted when both analogreset and digital reset are 0, but digitalreset_stat is 1 (deasserted after several cycle).
5. I can't checked this yet for now, because i'm using the FPGA on intel Devcloud.
Also, I found another problem. The digitalreset seems to be triggered repeatedly after the first reset, is there any guideline to troubleshoot the rst_controller?
