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Vijayvithal's avatar
Vijayvithal
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9 months ago

PCIe Gen2 on Cyclone V GT FPGA Dev Kit

I modified the altera_pcie/altera_pcie_hip_ast_ed/example_design/cv/pcie_de_gen1_x4_ast64.qsys file to support gen2 x4 I generated and compiled the code and tried loading it on the devkit. While th...
Board Debug
Vijayvithal's avatar
Vijayvithal
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9 months ago

The device is 5CGT–D9-C7N https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/cyclone/v-gt.html
The signals after running `echo 1 |sudo tee /sys/bus/pci/rescan`

I am connecting to the remote machine via the following steps

```

ssh -L 1309:localhost:1309 remote

nohup jtagd

```

on local machine I am running `jtagconfig` to update the connection

After a reboot of remote machine I am not able to trigger a capture because signaltap reports invalid JTAG configuration

Vijayvithal's avatar
Vijayvithal
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9 months ago

Attaching the project archive file for reference.

  • Wincent_Altera's avatar
    Wincent_Altera
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    9 months ago

    Hi Vijay,

    May I know is this gen2 (fail) design or gen1 ?
    What is the version of Quartus you use to compile this design ?

    Regards,
    Wincent_Altera

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      9 months ago

      Hi Vijay,

      Any update ? Hope to hear back from you so that we can proceed further.

      Regards,

      Wincent_Altera