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Vijayvithal's avatar
Vijayvithal
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9 months ago

PCIe Gen2 on Cyclone V GT FPGA Dev Kit

I modified the altera_pcie/altera_pcie_hip_ast_ed/example_design/cv/pcie_de_gen1_x4_ast64.qsys file to support gen2 x4 I generated and compiled the code and tried loading it on the devkit. While th...
Board Debug
Vijayvithal's avatar
Vijayvithal
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9 months ago

The device is 5CGT–D9-C7N https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/cyclone/v-gt.html
The signals after running `echo 1 |sudo tee /sys/bus/pci/rescan`

I am connecting to the remote machine via the following steps

```

ssh -L 1309:localhost:1309 remote

nohup jtagd

```

on local machine I am running `jtagconfig` to update the connection

After a reboot of remote machine I am not able to trigger a capture because signaltap reports invalid JTAG configuration

  • Vijayvithal's avatar
    Vijayvithal
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    9 months ago

    Attaching the project archive file for reference.

    • Wincent_Altera's avatar
      Wincent_Altera
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      9 months ago

      Hi Vijay,

      May I know is this gen2 (fail) design or gen1 ?
      What is the version of Quartus you use to compile this design ?

      Regards,
      Wincent_Altera

      • Wincent_Altera's avatar
        Wincent_Altera
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        9 months ago

        Hi Vijay,

        Any update ? Hope to hear back from you so that we can proceed further.

        Regards,

        Wincent_Altera

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    9 months ago

    Hi Vijay,

    I seeing your ltssm is stuck at 00h which is in detect.quiet stage.
    This mostly happen due to the host Can't detect far end Receiver.

    I suggest to check with the Connectivity problem or Board component problem/

    1. Is this plug in to slot that supported gen2 ?
    2. do you change the BIOS setting from "auto" to "gen2"
    3. Please check your VCCR/VCCT , ensure that it is 1.1v

    Regards,
    Wincent_Altera

    • Vijayvithal's avatar
      Vijayvithal
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      9 months ago

      Wincent,
      The board is plugged into gen4 pcie slot.

      Regarding the pin assignments,

      The Board reference manual recommends PCML for the serdes pins.

      We are currently using this setting

      set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
      set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
      set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
      set_instance_assignment -name IO_STANDARD LVDS -to clk_clk
      set_instance_assignment -name IO_STANDARD HCSL -to dut_refclk_clk
      set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dut_npor_pin_perst
      set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to dut_hip_serial_rx_in0
      set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to dut_hip_serial_rx_in1
      set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to dut_hip_serial_rx_in2
      set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to dut_hip_serial_rx_in3
      set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to dut_hip_serial_tx_out0
      set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to dut_hip_serial_tx_out1
      set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to dut_hip_serial_tx_out2
      set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to dut_hip_serial_tx_out3
      set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top