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Vijayvithal
New Contributor
New ContributorPCIe Gen2 on Cyclone V GT FPGA Dev Kit
I modified the altera_pcie/altera_pcie_hip_ast_ed/example_design/cv/pcie_de_gen1_x4_ast64.qsys file to support gen2 x4 I generated and compiled the code and tried loading it on the devkit. While th...
Wincent_Altera
Regular Contributor
Regular ContributorHi,
- May I know what is the device OPN that you are using ?
- Do you capture any .stp ? If not , do appreciate if you can do that, with that we can know where the LTSSM stuck at, hence further debug can be done.
- If you not sure how to capture that, please let me know, I can guide you step by step.
Regards,
Wincent_Altera
VijayvithalWhat is a device OPN?
I tried installing signaltap and capturing the boot sequence, but since I need to reboot the machine to get it to enumerate I did not make much progress there.
Please inform about the signals that I need to capture and I will do it.- Wincent_Altera
Hi Vijay
What is a device OPN? Is the device ordering number, just want to check if I could replicate this (ONLY IF i have the same device)
Example of device OPN https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/cyclone/v-gt.htmlPlease inform about the signals that I need to capture and I will do it.
- npor
- reset_status
- nreset_status
- pin_perstn
- current_speed
- dl_ltssm[4:0]
Regards,
Wincent_Altera
