Honored ContributorHi,
We are planning to use PCIe Gen-1 core on Stratix IV GX device. As per datasheet, minimum Application/core clock is 62.5 MHz. Is it possible, to reduce Application clock less than 62.5 MHz? Our system is working at 40 MHz. Rgds, Parag+
Honored ContributorI doubt Altera will support you if you chose to run the core below the minimum clock speed.
Can you not increase the frequency of your system, or part of your system to ensure you comply with the minimum frequency? Cheers, AlexHonored ContributorI agree. There is probably a good reason why there is a minimum clock frequency for the core. You could use a 62.5MHz clock for the core and keep using 40MHz for your design if you absolutely need to, you will just have to be careful with any signal crossing the clock domains, for example by using double clock fifos.
Honored ContributorIIRC the 'Application clock' from the PCIe block is the clock that it's application side logic (Avalon (etc) interface) runs at.
If you clock your logic from a different clock then qsys will (silently) add the appropriate clock crossing bridges.Honored ContributorThanks Alex,
We are porting ASIC in FPGA and meeting System clock more than 62.5 MHz is really impossible. I have started thinking towards SHIM designs which is used to lower down the RATE. Anybody used it ? Rgds, Parag+
