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Altera_Forum
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12 years ago

PCIe Gen-1 Application clock

Hi, We are planning to use PCIe Gen-1 core on Stratix IV GX device. As per datasheet, minimum Application/core clock is 62.5 MHz. Is it possible, to reduce Application clock less than 62.5 MHz?...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thanks Alex,

We are porting ASIC in FPGA and meeting System clock more than 62.5 MHz is really impossible. I have started thinking towards SHIM designs which is used to lower down the RATE. Anybody used it ?

Rgds,

Parag+