Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorPCIe Gen-1 Application clock
Hi, We are planning to use PCIe Gen-1 core on Stratix IV GX device. As per datasheet, minimum Application/core clock is 62.5 MHz. Is it possible, to reduce Application clock less than 62.5 MHz?...
Altera_ForumHonored Contributor
Honored ContributorIIRC the 'Application clock' from the PCIe block is the clock that it's application side logic (Avalon (etc) interface) runs at.
If you clock your logic from a different clock then qsys will (silently) add the appropriate clock crossing bridges.
