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Altera_Forum's avatar
Altera_Forum
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16 years ago

PCI interrupts

Hi All,

We have used SOPC builder to add a conventional PCI component to our SOPC system. The system makes use of the Intan interrupt pin.

My question is how do you actually generate a PCI interrupt? There does not seem to be any input on the Avalon side to request that a PCI interrupt is generated. I gave connected the Intan output of the component directly to the Inta# pin on the PCI connector. Do I need to add custom logic to generate the Interrupt and ignore the Intan output from the SOPC component?

We are using Quartus and SOPC builder 9.1

Many thanks

Vern

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi Vern,

    do you use the Altera PCI compiler for your component ?

    HJS
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi HJS,

    Yes, we use the Altera PCI compiler but built through SOPC builder rather than the mega-function wizard. I beleive that limits the avaliable options some what.

    We have made some good progress by controlling the INTA# pin from custom logic, effectively bypassing any control teh PCI core has over the interrrupt pin but are still curious as to how to use this pin from the core

    Many thanks

    Vern
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi Vern,

    if you want avalon components to generate PCI interrupts you have to add the Avalon CRA Port (Avalon Configuration Tab in the PCI Compiler). Then you will see an interrupt input to the PCI core. You can either trigger a PCI interrupt by writing to one of the Avalon to PCI mailboxes or by generating an avalon interrupt. You have to enable the interrupts in the PCI Interrupt Enable Register. The registers are described in the PCI Compiler guide.

    Regards,

    HJS
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi HJS,

    Oh, thats what the CRA port does! Tried it, fixed it, moved on :)

    Many thanks for your help

    Vern
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    hi ,

    am using cyclone IV qsys "ip compiler for pci express" ,if we enable CRA avalon slave port in parameter setting, then if i export CRA am not seeing any cra_irq in instance generated , but cra_irq (output) is only visible in system inspector , how to access that cra_irq, it is output but u mentioned interrupt input to the pci core will available .

    same happened when i used the single DW completer , rxm_irq (input) is visible in system inspector not visible in system content tab in qsys. how to use that rxm_irq

    also help me where mailbox registers available, and how to use write to it, in user guide they had given a2p_mailbox and p2a_mailbox with some address ,where to write those addresses, help me . If any reference design for interrupt or tutorial help me.

    thanks,

    santhosh
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Hi Guys,

    Anyone is successful in using Mailbox registers to generate interrupts to the Host?

    Iam using Arria10 FPGA and the application interface as "Avalon-MM with DMA", does this support mailbox registers?

    Request to please share on how to write into these a2p_mailbox and p2a_mailbox registers and how to enable the interrupts?

    Hi vernmid,

    Please share how does the CRA port helped to fix this issue?

    Thanks.

    Regards

    linus_alt