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Honored Contributor
Honored ContributorPassive Serial Tri-state
I am designing a Cyclone IV based board with an SPI interface that we would like to use to configure the FPGA with an MCU. We will configure the pins to toggle like Figure 8-16 (Device Handbook Vol ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- In our system, we employ a NIOSII processor. So ideally we could create a single RBF composed of SOF and ELF data then load that over the PS interface. --- Quote End --- No, the PS interface is only for the FPGA configuration data, eg., SOF file. If you had an ELF image that was supposed to go into on-chip RAM, then that would be part of the SOF image (via a .mif or .hex file). --- Quote Start --- Presently, we do something similar over JTAG with the "nios2-configure-sof" and "nios2-download" command from shell... --- Quote End --- Right, the first configures the FPGA, and the second downloads code to "somewhere". If that "somewhere" is off-chip SRAM, then it does not make sense to make it part of the RBF file. Does that make sense? Cheers, Dave
