pass generic value to a vhdl file in verilog

test_interface test_interface(

.interface_clk(clk),

.interface_frame_n(frame_n),

.interface_reset_n(reset_n),

.interface_ad(ad),

.data(data)

);

defparam test_interface.ioport = 16'h0080;

This is how parameters are passed in Verilog. I have not tried it with VHDL objects though.